diff options
Diffstat (limited to 'src/platforms')
| -rw-r--r-- | src/platforms/esp32/RGB_HUB75_PINS.png | bin | 0 -> 10405 bytes | |||
| -rw-r--r-- | src/platforms/esp32/esp32_i2s_parallel_dma.cpp | 6 | ||||
| -rw-r--r-- | src/platforms/esp32/esp32_i2s_parallel_dma.hpp | 6 | ||||
| -rw-r--r-- | src/platforms/esp32s3/gdma_lcd_parallel16.cpp | 38 | ||||
| -rw-r--r-- | src/platforms/esp32s3/gdma_lcd_parallel16.hpp | 5 |
5 files changed, 40 insertions, 15 deletions
diff --git a/src/platforms/esp32/RGB_HUB75_PINS.png b/src/platforms/esp32/RGB_HUB75_PINS.png Binary files differnew file mode 100644 index 0000000..2dc609e --- /dev/null +++ b/src/platforms/esp32/RGB_HUB75_PINS.png diff --git a/src/platforms/esp32/esp32_i2s_parallel_dma.cpp b/src/platforms/esp32/esp32_i2s_parallel_dma.cpp index 6b64200..f74274e 100644 --- a/src/platforms/esp32/esp32_i2s_parallel_dma.cpp +++ b/src/platforms/esp32/esp32_i2s_parallel_dma.cpp @@ -291,7 +291,7 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default) ///auto _div_num = 80000000L/freq; - ESP_LOGD("ESP32", "i2s pll_d2_clock clkm_div_num is: %d", _div_num); + ESP_LOGD("ESP32", "i2s pll_d2_clock clkm_div_num is: %ld", _div_num); dev->clkm_conf.clka_en=1; // Use the 80mhz system clock (PLL_D2_CLK) when '0' dev->clkm_conf.clkm_div_a = 1; // Clock denominator @@ -304,7 +304,7 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default) output_freq = output_freq + 0; // work around arudino 'unused var' issue if debug isn't enabled. - ESP_LOGI("ESP32/S2", "Output frequency is %d Mhz??", (output_freq/1000000/i2s_parallel_get_memory_width(ESP32_I2S_DEVICE, 16))); + ESP_LOGI("ESP32/S2", "Output frequency is %ld Mhz??", (output_freq/1000000/i2s_parallel_get_memory_width(ESP32_I2S_DEVICE, 16))); // Setup i2s clock @@ -662,4 +662,4 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default) -#endif
\ No newline at end of file +#endif diff --git a/src/platforms/esp32/esp32_i2s_parallel_dma.hpp b/src/platforms/esp32/esp32_i2s_parallel_dma.hpp index 0fb68d2..dd6c1f3 100644 --- a/src/platforms/esp32/esp32_i2s_parallel_dma.hpp +++ b/src/platforms/esp32/esp32_i2s_parallel_dma.hpp @@ -49,7 +49,9 @@ Contributors: #define DMA_MAX (4096-4) -#define ESP32_I2S_DEVICE I2S_NUM_0 +#ifndef ESP32_I2S_DEVICE + #define ESP32_I2S_DEVICE I2S_NUM_0 +#endif // The type used for this SoC #define HUB75_DMA_DESCRIPTOR_T lldesc_t @@ -144,4 +146,4 @@ i2s_dev_t* getDev(); - };
\ No newline at end of file + }; diff --git a/src/platforms/esp32s3/gdma_lcd_parallel16.cpp b/src/platforms/esp32s3/gdma_lcd_parallel16.cpp index 314bb99..d773b55 100644 --- a/src/platforms/esp32s3/gdma_lcd_parallel16.cpp +++ b/src/platforms/esp32s3/gdma_lcd_parallel16.cpp @@ -30,8 +30,8 @@ // static const char* TAG = "gdma_lcd_parallel16"; //#endif - static int _dmadesc_a_idx = 0; - static int _dmadesc_b_idx = 0; + //static int _dmadesc_a_idx = 0; + //static int _dmadesc_b_idx = 0; dma_descriptor_t desc; // DMA descriptor for testing @@ -98,22 +98,44 @@ //LCD_CAM.lcd_clock.clk_en = 0; // Enable peripheral clock // LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W) - LCD_CAM.lcd_clock.lcd_clk_sel = 2; + LCD_CAM.lcd_clock.lcd_clk_sel = 3; // Use 160Mhz Clock Source + LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle - LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 0; // PCLK = CLK / (CLKCNT_N+1) + + LCD_CAM.lcd_clock.lcd_clkcnt_n = 1; // Should never be zero + + //LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 0; // PCLK = CLK / (CLKCNT_N+1) + LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 1; // PCLK = CLK / 1 (... so 160Mhz still) if (_cfg.psram_clk_override) // fastest speed I can get PSRAM to work before nothing shows { - LCD_CAM.lcd_clock.lcd_clkm_div_num = 4; + ESP_LOGI("S3", "DMA buffer is on PSRAM. Limiting clockspeed...."); + LCD_CAM.lcd_clock.lcd_clkm_div_num = 10; //16mhz is the fasted the Octal PSRAM can support it seems } else { + + auto freq = (_cfg.bus_freq); + + auto _div_num = 8; // 20Mhz + if (freq < 20000000L) + { + _div_num = 12; // 13Mhz + } + else if (freq > 20000000L) + { + _div_num = 6; // 26Mhz --- likely to have noise without a good connection + } + //LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num; - LCD_CAM.lcd_clock.lcd_clkm_div_num = 3; + LCD_CAM.lcd_clock.lcd_clkm_div_num = _div_num; //3; + } - ESP_LOGI("S3", "Clock divider is %d", LCD_CAM.lcd_clock.lcd_clkm_div_num); + ESP_LOGI("S3", "Clock divider is %d", LCD_CAM.lcd_clock.lcd_clkm_div_num); + + ESP_LOGD("S3", "Resulting output clock frequency: %ld Mhz", (160000000L/LCD_CAM.lcd_clock.lcd_clkm_div_num)); LCD_CAM.lcd_clock.lcd_clkm_div_a = 1; // 0/1 fractional divide @@ -441,4 +463,4 @@ } // end flip -#endif
\ No newline at end of file +#endif diff --git a/src/platforms/esp32s3/gdma_lcd_parallel16.hpp b/src/platforms/esp32s3/gdma_lcd_parallel16.hpp index 3cb94e8..3d47c22 100644 --- a/src/platforms/esp32s3/gdma_lcd_parallel16.hpp +++ b/src/platforms/esp32s3/gdma_lcd_parallel16.hpp @@ -157,8 +157,9 @@ gdma_channel_handle_t dma_chan; uint32_t _dmadesc_count = 0; // number of dma decriptors - // uint32_t _dmadesc_a_idx = 0; - //uint32_t _dmadesc_b_idx = 0; + + uint32_t _dmadesc_a_idx = 0; + uint32_t _dmadesc_b_idx = 0; HUB75_DMA_DESCRIPTOR_T* _dmadesc_a = nullptr; HUB75_DMA_DESCRIPTOR_T* _dmadesc_b = nullptr; |
